1. Field of the Invention
The present invention relates to an image display device and its drive circuit, and more particularly to a liquid-crystal display device and its drive circuit.
2. Description of the Related Art
An active matrix display, which is represented by an active matrix liquid-crystal display, forms a thin-film transistor (hereinafter referred to as the TFT) for each pixel, and stores display information in each pixel to display an image. A polysilicon TFT is formed by using a polysilicon film that is polycrystallized by laser-annealing an amorphous silicon film to raise the mobility to approximately 100 cm2/V-s. A circuit composed of a polysilicon TFT operates from a signal having a frequency of up to several megahertz to several tens of megahertz. Therefore, not only pixels but also drive circuits such as a data driver for generating a video signal and a gate driver for performing a scan can be formed in the same process as for a TFT that composes a pixel on a substrate for a liquid-crystal display device or the like.
A transmissive liquid-crystal display displays an image by controlling the transmissivity of the light transmitted through a backlight. On the other hand, a reflective liquid-crystal display has a reflective electrode within a pixel to reflect extraneous light and displays an image by controlling the reflectivity of sunlight and room illumination light incident on the pixel. Therefore, the reflective liquid-crystal display does not require the backlight.
A liquid-crystal display having both the transmission function and reflection function is called a semi-transmissive liquid-crystal display. The reflective liquid-crystal display and the semi-transmissive liquid-crystal display whose backlight is extinguished generally consume considerably less power than the transmissive liquid-crystal display, which needs to illuminate the backlight.
A liquid-crystal display having a built-in pixel memory is extremely low in power consumption. A normal liquid-crystal display having no built-in pixel memory temporarily retains an electrical charge in a capacitor within a pixel to keep the voltage to be applied to a liquid crystal. Therefore, even when a still picture is to be displayed, the normal liquid-crystal display having no built-in pixel memory needs to periodically refresh the voltage.
Consequently, even when a motion picture or still picture is displayed, a data line for transferring a data signal to a pixel needs to be constantly driven at several tens of kilohertz. Therefore, a considerable amount of power is consumed by the data line and a data driver for driving the data line. The liquid-crystal display having a built-in pixel memory, which is mainly designed for displaying a still picture, has a static memory in each pixel. Therefore, when displaying a still picture, the liquid-crystal display having a built-in pixel memory does not have to perform a refresh operation. Consequently, it is possible to completely save the power to be consumed by the data line and data driver.
FIG. 12 shows the configuration of a conventional display having a built-in memory. Pixel circuits 102, which use a thin-film transistor, are mounted on a glass substrate 101 and arranged in a matrix form. For the sake of brevity, FIG. 12 shows 2 (V)×2 (H) pixel circuits 102. In reality, however, the number of rows and the number of columns are generally larger than 100.
Each pixel circuit 102 includes a static memory 104 and a selector 105. The static memory 104 samples an image signal from the data line in synchronism with a scanning pulse from a gate line. The selector 105 applies to a display section liquid-crystal element LC an AC voltage that corresponds to the information stored in the static memory 104. Further, an oscillator circuit (OSC) 103 and a buffer circuit 108, which are made of a thin-film transistor, are mounted on the glass substrate 101. The oscillator circuit 103 and buffer circuit 108 supply AC voltages VLCa and VLCb to all pixel circuits 102. Voltages VLCa and VLCb are square-wave voltages that normally have a frequency of 30 to 60 Hz, and in opposite phase to each other.
A gate input G of the static memory 104 is connected to gate lines GL1, GL2. A data input D of the static memory 104 is connected to data lines DL1, DL2. A data driver 106 is connected to the data lines DL1, DL2. A gate driver 107 is connected to the gate lines GL1, GL2.
An image signal is serially input (Sig_IN) into the data driver 106 from the outside of the display. The data driver 106 can temporarily store the input image signal and parallelly output it to the data lines DL1, DL2. The gate driver 107 sequentially outputs to the gate lines GL1, GL2 the pulses synchronized with the signal timing of the outputs DL1, DL2 of the data driver 106, thereby specifying a horizontal row of pixel circuits 102 into which the image signal developed in the data lines DL1, DL2 should be written.
The static memory 104 uses the scanning pulse supplied to the gate line to be connected to read the image signal of the data line to be connected. The selector 105 selects supplied square-wave voltage VLCa or VLCb in accordance with a one-bit storage state in the static memory, and supplies the selected square-wave voltage to the liquid-crystal element LC.
For example, it is assumed that a liquid crystal for giving a normally white screen (giving a white screen when the applied AC voltage is low) and an optical structure necessary for giving a normally white screen are used.
When the selector 105 selects voltage VLCa, voltages of the same phase are applied to two electrodes that sandwich the liquid-crystal element LC. Therefore, the applied AC voltage is 0 V so that the liquid-crystal element LC gives a white screen. On the contrary, when the selector 105 selects voltage VLCb, voltages in opposite phase to each other are applied to the two electrodes that sandwich the liquid-crystal element LC. Therefore, a raised AC voltage is applied so as to give a black screen. The liquid-crystal display having a built-in memory is described in more detail in JP-A-1996-194205 and JP-A-1996-286170.
The status (white or black) of each pixel can be determined by the storage state of the static memory 104. Therefore, while a still picture, which does not require an image refresh, is displayed, the operations of the data driver 106 and gate driver 107 can be stopped. This makes it possible to save the entire drive circuit power consumption for driving the data lines DL1, DL2 and gate lines GL1, GL2. Consequently, the liquid-crystal display having a built-in memory can substantially reduce the power consumption for a still picture display period unlike a normal liquid-crystal display.
Meanwhile, the power supply voltage for a circuit formed with a thin-film transistor is generally higher than that for an LSI or other circuit formed with monocrystalline silicon. Therefore, it may be necessary in some cases that a plurality of thin-film-transistor-based level shifters (LS) 109 be mounted on the glass substrate 101. The level shifters 109 voltage-amplify a small-amplitude voltage signal, which is supplied from an LSI that is positioned outside an image display, to a large-amplitude voltage signal, and supply drive signals to the data driver 106 and gate driver 107.
FIG. 13 shows a level shifter having a shutdown function. A grounded-gate amplifier circuit is formed by an n-channel TFT 111 and a load resistor 112. The symbol VDD represents a plus side power supply. An enable signal ENB for controlling the ON/OFF status of the TFT 111 enters a gate for the TFT 111. If the enable signal ENB has a voltage that is high enough to turn ON the TFT 111, a drain current adequate for performing a voltage amplification operation flows to the TFT 111. Therefore, a small-amplitude signal L-Sig is amplified to a large-amplitude signal Sig.
If, on the other hand, the enable signal ENB has a voltage that is low enough to turn OFF the TFT 111, the drain current flow to the TFT 111 is virtually zero. Therefore, the level shifter shown in FIG. 13 does not perform an amplification operation and reduces the power consumption to virtually zero. In other words, the level shifter shuts down.
FIG. 14 shows a conventional circuit configuration of a group of hierarchical level shifters. The output of a constantly operating level shifter (LS′) 121 is connected to enable inputs of the group of the level shifters 122. The level shifter 121 amplifies an input small-amplitude enable signal L-ENB to a large-amplitude enable signal ENB. The large-amplitude enable signal ENB determines the operating status/shutdown status of the group of level shifters 122. If the enable signal ENB is valid, the group of level shifters 122 amplifies small-amplitude signals L-Sig1 to L-Sig5 to large-amplitude signals Sig1 to Sig5. If, on the other hand, the enable signal ENB is not valid, the group of level shifters 122 stops their amplification operations. This configuration ensures that the small-amplitude enable signal L-ENB shuts down the group of level shifters 122 when the group of level shifters 122 need not be operated. Therefore, the power consumption of the group of level shifters 122 can be reduced. The circuit configuration of the group of hierarchical level shifters, which has been described above, is described in more detail in International Publication No. WO03/036606.